Date of Award

Summer 2015

Document Type

Thesis

Degree Name

Master of Science (MS)

Department

Electrical and Computer Engineering

First Advisor

Demerdash, Nabeel A. O.

Second Advisor

Skibinski, Gary L.

Third Advisor

Weise, Nathan

Abstract

Over the last several decades, there has been consistent growth in the research and development of multilevel voltage-source inverter-based adjustable speed motor drives (ASDs) as a result of low cost, high reliability power semiconductors. The three-level neutral-point-clamped (NPC) ASD is a popular multilevel inverter used in low and medium voltage applications because of its ability to produce lower levels of total harmonic distortion (THD) and withstand higher voltages while preserving the rated output power compared to two-level ASDs. As with other voltage-source inverters, three-level NPC ASDs produce common-mode voltage (CMV) that can cause motor shaft voltages, bearing currents, and excess voltage stresses on motor windings, resulting in the deterioration of motor bearings and insulation. Furthermore, the CMV and resultant currents can generate electromagnetic interference that can hinder the operation of sensitive control electronics. In this thesis, three carrier-based, three-level pulse-width-modulation (PWM) strategies were investigated to examine the levels of CMV, common-mode current, and dv/dt produced by the three-level NPC ASD. Additionally, the effects that each PWM strategy has on the THD in the output waveforms, as well as the total switching and conduction losses were analyzed through software simulation programs using a resistive-inductive load over a range of modulation indices. The first of the three methods, in-phase disposition sub-harmonic PWM (PD-SPWM), was verified experimentally using a laboratory-scale, 7.5 kVA three-level NPC ASD prototype. It was determined that PD-SPWM produced the highest CMV amplitude of one-third the dc bus voltage, but the lowest values of differential-mode dv/dt, THD, and drive losses. The second strategy, phase-opposition (PO)-SPWM, reduced the CMV amplitude to one-sixth the dc bus voltage, at the cost of higher THD and drive losses and a doubling of the differential-mode dv/dt. The final strategy, zero common-mode (ZCM)-SPWM, was modified (MZCM-SPWM) to accommodate IGBT dead-time by delaying the output voltage transitions based on the polarity of the output currents and the direction of the commanded voltage transitions. The MZCM-SPWM method nearly eliminated all CMV pulses while maintaining comparable levels of THD, but produced twice the switching losses compared to PD- and PO- SPWM, and twice the differential-mode dv/dt compared to PD-SPWM.

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