A New Scalable Fault Tolerant Routing Algorithm for Networks-on-Chip
Institute of Electrical and Electronics Engineers (IEEE)
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)
In this paper we propose a distributed routing algorithm for networks-on-chip (NoCs) that can dynamically detect permanent failures in NoC links and recalculate routing paths using healthy links. What sets the proposed methodology apart from the previous works is that it provides a better tradeoff point between the improvement in fault tolerance and performance penalty due to the required redundancy and extra logic. An NoC prototype is implemented and simulated in Verilog-HDL to show the correct operation of the proposed adaptive routing.