Date of Award

Spring 1997

Document Type

Thesis - Restricted

Degree Name

Master of Science (MS)


Computer Science

First Advisor

Belfore, Lee A.

Second Advisor

Heinen, James

Third Advisor

Feng, Xing


This work was done in an attempt to fill a need in the manufacture of WSI and VLSI Artificial Neural Networks (ANN). That need is the development of efficient test procedures for testing WSI and VLSI ANN implementations. As will be shown in this work, the current test procedures are limited in their coverage of the ANN components or are limited to specific types of ANN architectures. The Low Activation Gain Fault Detection (LAGFD) test algorithm presented in this work assumes no particular network architecture. The only requirements of the algorithm is that the ANN interconnection matrix be programmable and fully connectable, and that the activation function of each neuron be programmable to a low value, i.e. G * u < l. The LAGFD algorithm is shown to be implementable as a Built-in Self Test (BIST) to be included directly on the silicon ANN implementation



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