Document Type

Article

Language

eng

Publication Date

12-22-2010

Publisher

Institute of Physics

Source Publication

Nanotechnology

Source ISSN

0957-4484

Original Item ID

doi: 10.1088/0957-4484/22/5/055704

Abstract

Integrated freestanding single-crystal silicon nanowires with typical dimension of 100 nm × 100 nm × 5 µm are fabricated by conventional 1:1 optical lithography and wet chemical silicon etching. The fabrication procedure can lead to wafer-scale integration of silicon nanowires in arrays. The measured electrical transport characteristics of the silicon nanowires covered with/without SiO2 support a model of Fermi level pinning near the conduction band. The I–V curves of the nanowires reveal a current carrier polarity reversal depending on Si–SiO2 and Si–H bonds on the nanowire surfaces

Comments

Accepted version. Nanotechnology, Vol. 22, No. 5 (December 2010). DOI. © Institute of Physics 2010. Used with permission.

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