Document Type
Conference Proceeding
Language
eng
Format of Original
6 p.
Publication Date
9-2014
Publisher
Institute of Electrical and Electronics Engineers
Source Publication
2014 27th IEEE International System-on-Chip Conference (SOCC)
Original Item ID
doi: 10.1109/SOCC.2014.6948937
Abstract
Power consumption remains one of the most important design objectives for network-on-chip (NoC) based systems. In this paper, we focus on the NoC component of these systems. Specifically, we introduce a new distributed dynamic voltage and frequency scaling (DVFS) algorithm that can tune the operation frequency and supply voltage of each router in the NoC dynamically in response to network load trends in order to mitigate network congestion and to reduce power consumption. The proposed distributed DVFS algorithm uses history based predictors that predict link and buffer utilizations. These predictions are used to forecast the future network load, which is used to also do proactive frequency tuning, thereby addressing potential congestion issues and reducing power consumption. When frequency throttle is used only, power consumption is reduced by up to 50% while the network latency is only slightly degraded. When frequency boost is also used, in addition to significant power reductions, network latency is also improved. We utilize the proposed DVFS algorithm as a testbed to gain new insights into the potential of DVFS for NoCs at router level.
Recommended Citation
Ababei, Cristinel and Mastronarde, Nicholas, "Benefits and Costs of Prediction Based DVFS for NoCs at Router Level" (2014). Electrical and Computer Engineering Faculty Research and Publications. 78.
https://epublications.marquette.edu/electric_fac/78
Comments
Accepted version. Published as part of the proceedings of the conference, 2014 27th IEEE International System-on-Chip Conference (SOCC), 2014: 255 - 260. DOI. © 2014 [Institute of Electrical and Electronics Engineers (IEEE). Used with permission.