Institute of Electrical and Electronics Engineers (IEEE)
2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)
In this paper, we present the design and verification of the H.264 video decoder algorithm on FPGAs. The primary difference compared to previously reported designs is that the communication between the decoder modules is done via a network-on-chip in our case. The proposed design is a complete system level hardware design described in VHDL and Verilog. We report experimental results for two different implementations. The first implementation uses a 3×3 network-on-chip and is validated on the DE4 development board, which uses Altera's Stratix IV GX FPGA chip. The second implementation uses a 2×2 network-on-chip and is validated on the Cyclone V SoC FPGA, which is a smaller FPGA chip available on the DE1-SoC board. Both implementations will be released to the public domain with the hope that they will foster further research, in addition to facilitating replication and comparison to our results.
Barge, Ian and Ababei, Cristinel, "H.264 Video Decoder Implemented on Fpgas Using 3×3 And 2×2 Networks-On-Chip" (2018). Electrical and Computer Engineering Faculty Research and Publications. 315.
Accepted version."H.264 video decoder implemented on FPGAs using 3×3 and 2×2 networks-on-chip," published in 2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 4-6 Dec. 2017. DOI. © 2018 IEEE. Used with permission.