Institute of Electrical and Electronics Engineers (IEEE)
2017 2nd International Conference on Communication Systems, Computing and IT Applications (CSCITA)
Chip functionality testing can greatly benefit from a Built In Self-Test (BIST). The Self-Test Using MISR and Parallel Shift Register Sequence Generator (STUMPS) architecture uses a compression technique to generate a set of test patterns, to submit them to the circuit undergoing testing, and to compare the output with that of a “gold” (known to be good circuit) by loading and comparing the contents of a Multiple Input Shift Register (MISR). We propose to use algebraic signatures as the comparison signature implemented by the MISR. As we will see, the MISR is still basically a Linear Feedback Shift Register (LFSR), but can now be made to guarantee to discover one or up to k output discrepancies, where k is a very small number that determines the length of the MISR register. The construction of the algebraic signature register is generic and only the comparison value needs to be programmed.
Jeswani, Jaya; Rose, John; and Schwarz, Thomas, "Using Algebraic Signatures to Compress Built-in Self Test on a Chip" (2017). Mathematics, Statistics and Computer Science Faculty Research and Publications. 554.
Accepted version. Published as part of the proceedings of the 2017 2nd International Conference on Communication Systems, Computing and IT Applications (CSCITA): 95-100. DOI. © 2017 IEEE. Used with permission.