Date of Award

Spring 1965

Document Type

Thesis - Restricted

Degree Name

Master of Science (MS)


Electrical Engineering

First Advisor

Ishii, Koryu T.

Second Advisor

Battocletti, J. H.

Third Advisor

Horgan J. D.


The design of transistor circuits with bias stability of a specified tolerance is a complicated electrical engineering problem. The mathematics of an exact solution becomes quite tedious and over-simplification degrades the results. The transistor parameters which affect the operating point have wide tolerances and vary as a function of operating conditions. This thesis is the description and analysis of a breadboard designed and constructed by the author which simulates a PNP transistor for DC operation. The three parameters "formula" which determine the operating point are variable over a range adequate to simulate the majority of low power level transistor types. To analyze a circuit design its components are connected to the terminals of the transistor simulator bread, board representing the collector, base, and emitter of a transistor; and the controls are adjusted to represent worst-case conditions. The extreme variations of the operating, point are determined by measuring the simulated values of collector current and voltage. The compliments of circuits using NPN transistors can be used in their evaluation. Thus, the transistor simulator is a special purpose analog computer for the solution of bias circuit equations. Letter symbols used in this thesis are those recommended by the Joint Electron Device Engineering Councils (JEDEC).



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