A Case for Heterogeneous Network-on-Chip Based H.264 Video Decoders

Authors

Milad Ghorbani Moghaddam, Marquette University
Cristinel Ababei, Marquette UniversityFollow

Document Type

Article

Publication Date

2019

Publisher

Association for Computing Machinery (ACM)

Source Publication

GLSVLSI '19: Proceedings of the 2019 on Great Lakes Symposium on VLSI

Source ISSN

9781450362528

Abstract

The design of a heterogeneous network-on-chip (NoC) based H.264 video decoder is proposed. A thorough investigation using a system simulator developed as the combination of a cycle accurate NoC simulator together with complete implementations of all the video decoder modules is presented. The target hardware platform is a multicore system-on-chip, where the cores were designed for specific functions that correspond to the modules of the video decoder. Because such cores have different sizes and aspect ratios, a heterogeneous NoC is employed to facilitate the communication between modules. This is different from the reference case of a homogeneous NoC based hardware platform, where all cores are general purpose processors with the same area and where the NoC is a regular mesh NoC. The investigation looks at the impact of core sizes and floorplan for a given technology node as well as at the performance variation across several technology nodes.

Comments

GLSVLSI '19: Proceedings of the 2019 on Great Lakes Symposium on VLSI (May 2019): 263-266. DOI.

Recommended Citation

Moghaddam, Milad Ghorbani and Ababei, Cristinel, "A Case for Heterogeneous Network-on-Chip Based H.264 Video Decoders" (2019). Electrical and Computer Engineering Faculty Research and Publications. 697.
https://epublications.marquette.edu/electric_fac/697