Date of Award
Summer 1969
Document Type
Thesis - Restricted
Degree Name
Master of Science (MS)
Department
Electrical Engineering
First Advisor
Wang, K. C.
Abstract
An asynchronous unit delay (A.U.D.) is an asynchronous sequential circuit in which, the present value of the output n-tuple is equal to the value of the input n-tuple prior to the last input change. In the circuits that employ asynchronous unit delays as memory elements, it is logical to consider the input-output events by using the input changes as reference. An asynchronous sequential circuit is said to have finite memory, if its present output value depends only on a finite number of previous inputs and outputs. For any given asynchronous sequential circuit characterized by a flow table, necessary and sufficient conditions for testing whether or not the circuit has finite memory are found. If a circuit has finite memory, the memory length is also determined. It is then shown that any circuit of finite memory can be realized in a canonical form by using asynchronous unit delays as memory elements. Techniques for eliminating transient outputs are also developed. Some related problems, such as the information lossless property of a circuit, and of realizing machines without finite memory by adding (redundant) outputs, are also studied.
Recommended Citation
Shipchandler, Tamim T., "Finite Memory Asynchronous Sequential Machines" (1969). Master's Theses (1922-2009) Access restricted to Marquette Campus. 4166.
https://epublications.marquette.edu/theses/4166