Date of Award
Spring 4-20-2026
Document Type
Thesis
Degree Name
Master of Science (MS)
Department
Electrical and Computer Engineering
First Advisor
Cristinel Ababei
Second Advisor
Fred Frigo
Third Advisor
Richard Povinelli
Abstract
This thesis presents a novel internet-of-things (IoT) edge device, EdgeCube, a compact embedded system that combines a microcontroller unit (MCU) and a field-programmable gate array (FPGA). The proposed platform explores a trade-off between the performance gains achievable through FPGA-based acceleration and the associated increases in cost and power consumption. The primary contributions of this thesis include (1) the design of a compact hybrid MCU–FPGA edge architecture intended for vision workloads, (2) a streaming MCU-to-FPGA data path using SPI for frame transfer, and (3) an end-to-end hardware prototype and evaluation on an embedded inference task. Designed for IoT vision applications, EdgeCube integrates an on-board camera (ESP32-CAM) and is demonstrated on the classic person detection problem, in which the device determines whether a person is present in each captured frame. This workload is representative of privacy-preserving edge sensing scenarios where only a one-bit decision is required (1 = person detected, 0 = no person detected), removing the need to transmit identifiable imagery and reducing communication overhead and energy usage. In EdgeCube, frames captured by the MCU are streamed to the FPGA, where a lightweight convolutional neural network (CNN) performs real-time inference on the received image data. Implementing the CNN on the FPGA enables low-latency inference by leveraging hardware parallelism and accelerator-style pipelining. A hardware prototype is developed using an ESP32-CAM MCU and an AMD Xilinx Artix-7 FPGA, with an ST SensorTile included to support additional sensing capabilities. Using 96×96 grayscale frames acquired from the OV2640 camera sensor, the proposed EdgeCube achieves 234 frames per second throughput with 71% detection accuracy, demonstrating that real-time embedded inference is feasible on a compact hybrid MCU–FPGA edge platform.